A frequency synthesizer, being a crucial constituent in a wireless communication system, is responsible for handling conversion between high frequency carrier waves and baseband signals. Therefore, a quality of signal conversion and overall performance of a transmission system are greatly dependent on a design quality of a frequency synthesizer. In a radio frequency (RF) wireless transmission system, a frequency synthesizer is generally realized by a phase-locked loop (PLL), which is currently dominated by sigma-delta (Σ-Δ) modulation fractional PLL structure; sigma-delta (Σ-Δ) modulation is a method for encoding analog signals into digital signals or higher-resolution digital signals into lower-resolution digital signals using error feedback, where the difference between the two signals is measured and used to improve the conversion. In such a structure, a fractional frequency dividing circuit is formed by integrating a multiple-modulus divider with a Σ-Δ modulator.
FIG. 1 shows a schematic diagram of a multiple-modulus divider 10 disclosed in a publication “IEEE, J. Solid-State Circuit” by S. Vaucher. The multiple-modulus divider 10 comprises eight dividers CE0 to CE7. A divisor is consisted of control signals P0 to P7. FIG. 2 shows an arbitrary divider CEn in FIG. 1, where n is an integer from 0 to 7. The divider CEn divides an input frequency at a frequency input end FI by 2 or 3 to generate an output frequency at a frequency output end FO. A state of the divider CEn dividing by 2 or 3 is controlled by a control signal Pn at a control end PI and a modulus input signal MIn at a modulus input end MI. The multiple-modulus divider 10 in FIG. 1 performs frequency dividing according to a divisor on an input frequency at the frequency input end FI of the dividers CE0, so as to output a result at the modulus output end MO of the divider CE0. The multiple-modulus divider 10 is operable within a divisor range of 28 to 28+1−1.
In order to extend the operable divisor range in a way that a multiple-modulus divider adopting a single input frequency is able to accommodate frequency ranges of various application protocols, a divisor extension logic 12 is added as shown in FIG. 3 to form a multiple-modulus divider 14 that has an extended operable divisor range of 25 to 28+1−1. In FIG. 3, the divisor is consisted of control signals P0 to P8, one control signal for each respective divider. A number sequence [P8, P7, . . . , P0] is utilized as a divisor control P to represent logic values of the control signals P0 to P8. Briefly speaking, the divisor extension logic 12 selectively bypasses last several divisors according to a current divisor, such that frequency dividing is not provided for an input frequency FIN in equivalence. For example, for a divisor 63, the divisor control P is [000111111]. Since the control signals P6 to P8 are 0, a modulus input signal MI4 is fixed to 1, which means the dividers CE5 to CE7 are to be skipped, providing no frequency dividing effects during frequency generation. At this point, frequencies of modulus output signals MO0 to MO4 are the same, being approximately 1/63 of a signal frequency at the frequency input end FI of the dividers CE0.